In integrated circuit (IC) manufacturing, a semiconductor wafer typically contains a plurality of testlines in the scribe line region between adjacent semiconductor chips. Each testline includes a plurality of probe pads connected to a number of devices under test (DUTs), which are structures similar to those that are normally used in the integrated circuit products in the circuit region. DUTs are usually formed in the scribe line regions on a testline at the same time as the functional circuits using the same process steps. Probe pads are usually flat, square metal surfaces on a testline through which test stimuli can be applied to corresponding DUTs. Parametric test results on DUTs are usually utilized to monitor, improve and refine a semiconductor manufacturing process. Yield of test structures on a testline is often used to predict the yield of functional integrated circuits in the circuit region.
After manufacturing, the semiconductor wafer is sawed from the scribe line regions to separate the semiconductor chips, so that each of the semiconductor chips may be packaged individually. Therefore, the probe pads and DUTs in the scribe line regions are destroyed. After the dicing process, it is not possible to perform parametric tests on DUTs to predict the yield of functional integrated circuits in the circuit regions. The yield of individual semiconductor chips after dicing can not be accurately controlled.